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| CT2566 MIL-STD-1553 to Microprocessor Interface Unit Features * * * * * * * * * * Second Source Compatible to the BUS-66300 PGA Version available, (second source to the BUS-66312) Compatible with MIL-STD-1750 CPUs Compatible with MOTOROLA, INTEL, and ZILOG CPUs Compatible with Aeroflex's CT2565 BC/RT/MT and CT2512 RT Minimizes CPU overhead Signal controls for shared memory implementation Transfers complete messages to shared memory Provides memory mapped 1553 interface Packaging - Hermetic Metal * 78 Pin, 2.1" x 1.87" x .25" PGA type package * 82 Lead, 2.2" x 1.61 x .18" Flat Package CIRCUIT TECHNOLOGY www.aeroflex.com A E RO F LE X LA C ISO 9001 E RTIFIED B S I NC . Description Aeroflex CT2566 MIL-STD-1553 to Microprocessor Interface Unit simplifies the CPU to 1553 Data Bus interface. The CT2566 provides an interface by using RAM allowing the CPU to transmit or receive 1553 traffic simply by accessing the memory. All 1553 message transfers are entirely memory or I/O mapped. The CT2566 supports 1553 interface devices such as Aeroflex's CT2512 dual RT or the CT2565 dual BC, RT, and MT. The CT2566 operates over the full military -55C to +125C temperature range. CLOCK IN MSTRCLR SELECT STRBD READYD RD/WR MEM/REG EXTEN EXTLD CPU TIMING MEMORY TIMING IOEN BUSREQ BUSGRNT BUSACK CS OE WR MEMCS MEMOE MEMWR ADRINC NBGRNT BCSTART TAGEN EOM SOM BLOCK STATUS WORD MSGERR TIMEOUT STATERR LOOPERR CHB/CHA CTLINB/A CTLOUT B/A RTU/BC MT DBAC SSBUSY SSFLAG SVCREQ RESET CONTENTION RESOLVER MICROCODE CONTROLLER A15-A00 D15-D00 OPERATION CONTROL REGISTERS CONFIGURATION REGISTER START / RESET REGISTER INTERRUPT MASK REGISTER INT INTERRUPT GENERATOR Figure 1 - Functional Block Diagram eroflex Circuit Technology - Data Bus Modules For The Future (c) SCDCT2566 REV B 8/10/99 PARAMETER Specifications at Nominal Power Supply Voltages VALUE -630 -700 UNITS Logic IIH (With VIH = 2.7V) IIL (With VIL = 0.0V) IOH IOL VIH VIL VOH VOL Clock Power Supplies Voltage Current Drain Temperature Range Operating (Case) Storage Physical Characteristics Size 78 pin DIP 82 pin flatpack Weight 78 pin DIP 82 pin flatpack A A mA mA V V V V MHz V mA C C 4.0 min 4.0 2.0 0.8 3.7 0.4 12 5.010% 10 typ -55 to +125 -65 to +150 2.1 x 1.87 x 0.25 (53 x 47.5 x 6.4) 2.1 x 1.87 x 0.25 (55.6 x 40.6 x 3.71) 1 (28) 1 (28) in (mm) in (mm) oz (g) oz (g) Table 1 - Specifications GENERAL The CT2566 was designed to perform required handshaking to the 1553 interface device, storing or retrieving message(s) from a user supplied RAM and notifying the CPU that a 1553 transaction has occurred. The CPU uses this RAM to read the received data as well as to store messages to be transmitted onto the Bus. The CT2566 can be used to implement BC, RT, or MT operation and can be either memory mapped or I/O mapped to CPU address space. Registers internal to the CT2566 control its operation. The CT2566 can access up to four external, user supplied registers and can address up to 64K words of RAM. The RAM selected must be a non-latched static RAM (capable of meeting the timing constraints for the CT2566). A double Aeroflex Circuit Technology buffering architecture is provided to prevent incomplete or partially updated information from being transmitted onto the 1553 Data Bus. The CT2566 requires an external, user supplied clock. COMPATIBLE MICROPROCESSOR TYPES The CT2566 may be used with most common microprocessors, including, the Motorola 68000 family, the Intel 8080 family, Zilog Z8000 products, and available MIL-STD-1750 processors. Interfacing the CT2566 to the 1553 Data Bus requires external circuitry such as Aeroflex's CT2565(BC/RT/MT) and ACT4489D transceivers. Figure 2 shows the interconnection for these components. 2 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME SELECT RD/WR READYD EXTEN TAGEN EOM SOM STATERR ADRINC MEM/REG CLOCK IN LOOPERR BUSREQ BUSGRNT I/O I I O O O I I I I I I I I O DESCRIPTION Select. When active, selects CT2566 for operation. Read/Write. Controls CPU bus data direction. Ready Data. When active indicates data has been received from, or is available to the CPU. External Enable. Output from CT2566 to enable output from external devices. Same timing as MEMOE. Tag Enable. Enables an external time tag counter for transferring the time tag word into memory. End of Message. Input from 1553 device indicating end of message. Start of Message. Input from 1553 device indicating start of message in RTU mode. Status Error. Input from 1553 device when status word has either a bit set or unexpected RT address (in BC mode only). Address Increment. Sent from 1553 device to increment address counter following word transfer. Memory/Register. Input from CPU to select memory or register data transfer. Clock input; 50% duty cycle, 12MHz, max. Loop Error. Input from 1553 device if short loop BIT fails. Bus Request. When active, indicates 1553 device requires use of the address/data bus. Bus Grant. Handshake output to 1553 device in response to BUS REQUEST indicating address/data bus available to 1553 device. Memory Chip Select. Low from CT2566 to enable external RAM. Used with 4K x 4 RAM type device to read RAM or used in conjunction with MEMWR to write data into RAM. Output Enable. Input from 1553 device used to enable memory on the parallel bus. Not Used. Low pulse from 1553 device preceding start of received new protocol sequence. Used with superseding command to reset DMA in progress. Logic power supply. Data Bus Bit 15 (MSB). Data Bus Bit 13. Data Bus Bit 11. Data Bus Bit 9. Data Bus Bit 7. Data Bus Bit 5. Data Bus Bit 3. 15 16 Not Used MEMCS O 17 18 19 OE N/C NBGRNT I I 20 21 22 23 24 25 26 27 + 5 Volt D15 D13 D11 D09 D07 D05 D03 I I/O I/O I/O I/O I/O I/O I/O Table 2 - Pin Functions (78 Pin DIP) 3 Aeroflex Circuit Technology SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 PIN NO. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NAME D01 SSFLAG SSBUSY RTU/BC A14 A12 A10 A08 A06 A04 A02 A00 GND STRBD IOEN I/O I/O O O O O O O O O O I/O I/O I O DESCRIPTION Data Bus Bit 1. Subsystem Flag. Output to 1553 device to set RT subsystem flag status bit. Subsystem Busy. Output to 1553 device to set RT subsystem busy flag. Output to 1553 device used in conjunction with MT to set operating mode. Address Bit 14. Address Bit 12. Address Bit 10. Address Bit 8. Address Bit 6. Address Bit 4. Address Bit 2. Address Bit 0 (LSB). Signal Return. Strobe Data. Used in conjunction with SELECT to indicate a data transfer cycle to/from CPU. Input/Output Enable. Output from CT2566 to enable external buffers/latches connecting the hybrid to the address/data bus. External Load. Used to load data into external device via the CT2566 data bus. Same timing as MEMWR. Input from 1553 in RT mode used to indicate received 1553 message came in either Channel A or B. Interrupt. Interrupt pulse line to CPU. Bus Controller Start. Outputs to 1553 in initiate BC cycle. Reset. Output to external device from CT2566 consisting of the OR condition of CPU reset and CPU Master Clear. Message Error. Input from 1553 device when an error occurs in message sequence. Input to change active memory map area (0 = area A). Output from CT2566 selecting which area is to be active (0 = area A). Input from 1553 device indicating no response time-out. Master Clear. Power-on reset from CPU. Resets DMA in progress and internal registers to logic "0". Bus Acknowledge. Input from 1553 device acknowledge receipt of BUSGRNT. Write. Input from 1553 device for writing data into memory. Chip Select. Input from 1553 device that is routed to MEMCS. 43 44 45 46 47 48 49 50 51 52 53 54 55 EXTLD CHB/CHA INT BCSTART RESET MSGERR CTLIN B/A CTLOUT B/A TIMEOUT MSTRCLR BUSACK WR CS O O O O I I O I I I I I Table 2 - Pin Functions (78 Pin DIP) (Cont.) Aeroflex Circuit Technology 4 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 PIN NO. 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 NAME MEMOE MEMWR Not Used MT D14 D12 D10 D08 D06 D04 D02 D00 SVCREQ DBAC A15 A13 A11 A09 A07 A05 A03 A01 GND I/O O O O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O I/O - DESCRIPTION Memory Output Enable. Output from CT2566 to enable memory output data. Memory Write. Output pulse from CT2566 to write data bus data into memory. Bus Monitor. Used in conjunction with RTU/BC to set operating mode. Data Bus Bit 14. Data Bus Bit 12. Data Bus Bit 10. Data Bus Bit 8. Data Bus Bit 6. Data Bus Bit 4. Data Bus Bit 2. Data Bus Bit 0 (LSB). Service Request. Used to set service request bit in RT Status Word. Dynamic Bus Acceptance. Used to set status bit in RT Status Word. Address Bit 15 (MSB). Address Bit 13. Address Bit 11. Address Bit 9. Address Bit 7. Address Bit 5. Address Bit 3. Address Bit 1. Chassis Ground. Table 2 - Pin Functions (78 Pin DIP) (Cont.) PIN NO. 1 2 3 4 5 6 7 N/C SELECT STRBD RD/WR IOENBL READYD EXTLD FUNCTION PIN NO. 42 43 44 45 46 47 48 N/C GROUND CHASSIS GROUND A00 (LSB) A01 A02 A03 FUNCTION Table 3 - CT2566FP Pin Functions (82 Pin Flat Package) Aeroflex Circuit Technology 5 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 PIN NO. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 EXTEN CHB/CHA TAGEN INT EOM BCSTART SOM RESET STATERR MSGERR ADRINC CTLIN B/A MEM/REG FUNCTION PIN NO. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 RTU/BC DBAC SSBUSY SVCREQ SSFLAG D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 N/C FUNCTION CTLOUT B/A CLOCK IN TIMEOUT LOOPERR MSTRCLR BUSYREQ BUSACK BUSGRNT WR N/C CS MEMCS MEMOE OE MEMWR Not Used N/C NBGRNT MT +5V N/C Table 3 - CT2566FP Pin Functions (82 Pin Flat Package) (Cont.) Aeroflex Circuit Technology 6 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 MEMORY MANAGEMENT The RAM used by the CT2566 can be any standard static memory with a WRITE STROBE pulse width requirement less than 70ns. The RAM area is broken down into pointers, look-up tables, and data blocks. All 1553 operation control is accomplished through the RAM, including fault monitoring and data block transfers. For most applications, a 4K x 16 memory is sufficient to store the number of messages, but the CT2566 can access up to 64K words. to ensure that the swapping of the current and non-current areas doesn't occur while the CT2566 is processing a message from the 1553 device. During message processing, the INCMD is a logic "0" and the CPU's map area selection is inhibited. CTLIN B/A will be automatically latched back into the CT2566 when INCMD and NODT change to a logic "1". DESCRIPTOR STACK The CT2566 uses a Descriptor Stack in BC and RTU modes. Each stack entry contains four words which refer to one 1553 message (See Figure 4). The Block Status Word, shown in Figure 5, indicates the physical bus which received the message (RTU mode), reports whether or not an error was detected during message transfer, and indicates whether the message was completed (SOM replaced with EOM). The user-supplied Time-Tag word is loaded at the start of a message transfer and is updated at the end of the transfer. The contents of the fourth word in the Descriptor Stack depends on the operating mode. In BC mode, it contains the address of the message data block containing the 1553 message formatted as shown in Figure 6. In RTU mode, the word contains the received 1553 Command Word as shown in Figure 7. A Stack Pointer must be initialized by the CPU. The Descriptor Stack contains 64, four word entries, and DOUBLE BUFFERING A Double Buffering system is available to prevent partially updated data blocks from being read by the CPU or transferred onto the 1553 Data Bus. To use Double Buffering the CPU must divide the RAM into two areas: "current" and "non-current". Two Stack Pointers, Descriptor Stacks, and Look-Up Tables are required to be used by the CPU. The 1553 device has access only to the current area of RAM, and will use the current Descriptor Stack and Look-Up Table. While the 1553 device is processing messages using the current area pointers, the CPU can be setting up the next set of messages in the non-current area of RAM. Once an EOM or BCEOM occurs, the CPU can swap the current and non-current areas by toggling bit 13 of the Configuration Register (See register section for description). The 1553 device will then have access to the new current area. Meanwhile, the CPU can begin processing the data received during the previous transfer or can begin setting up the next set of 1553 messages. BLOCK STATUS WORD TIME TAG WORD RESERVED MESSABE BLOCK ADDRESS BC DESCRIPTION BLOCK 50 CTLOUT B/A BUS-66300 D Q BLOCK STATUS WORD TIME TAG WORD RESERVED RECEIVED COMMAND WORD RTU DESCRIPTION BLOCK INCMD NODT 12 MHz LS74 C Q 49 CTLIN B/A Notes: (1) INCMD is from the BUS-65600 or BUS-65112. (2) CTLOUT B/A reflects bit 13 of the Configuration Register. (3) CTLIN B/A is used to select the current area. Figure 4 - Descriptor Stack Entries automatically wraps around (the 64th entry is followed by the first entry). The 1553 device uses the current area Stack Pointer to determine the address of the Stack entry to be used for the current 1553 message. The CT2566 automatically increments the current area Stack Pointer by four upon the completion of each Figure 3 - Synchronized map switching u the CT2566 An external circuit (shown in Figure 3) can be added Aeroflex Circuit Technology 7 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 message regardless of whether or not an error was detected during the processing of that message. LOOK-UP TABLES In RTU mode a Look-Up Table is provided to allow the CT2566 to store messages in distinct areas of RAM based upon the subaddress of the received command word. See RTU operation for details. The CT2566 uses the T/R and the five subaddress bits to form a pointer into the "current area" Look-Up Table. The first 32 words of this table are initialized by the user with the addresses of the data blocks to be used for receiving data into subaddress 0,1,2,...31. The next 32 words are initialized by the user with the address of the data blocks to be used when transmitting data from subaddress 0,1,2,...31. addition, the CT2566 can access up to four external, user supplied registers. Possible external register applications include: defining the RTU address, storing a CPU Time Tag, and reading a captured Built-In-Test (BIT) Word from the 1553 interface unit. For further information, consult factory. Table 2 - Internal Registers Address Definition CT2566 Address Bits A2 A1 A0 0 0 0 0 1 1 1 1 2 1 1 1 0 1 Definition Interrupt Mask Register Configuration Register Not Used Start/Reset Register (write only) External Register External Register External Register External Register 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CT2566 REGISTERS The CT2566 is controlled through the use of three internal registers: the Interrupt Mask Register, Configuration Register, and Start/Reset Register. In 15 14 13 12 11 10 9 8 7 1 6 1 5 1 4 1 3 1 SUBSYSTEM FLAG SERVICE REQUEST BUSY DB ACCEPT STOP ON ERROR CONTROL AREA BIT B/A MT RTU/BC BIT SUBSYSTEM FLAG SERVICE REQUEST BUSY DB ACCEPT STOP ON ERROR CONTROL AREA B/A RTU/BC/MT DEFINITIONS 1553 status word bit. 1553 status word bit. 1553 status word bit. 1553 status word bit. Causes BC to stop at the end of current data block if an error is detected. Used for double buffering (See Double Buffering). Operating Mode. Bit 15 Bit 14 0 0 0 1 1 0 1 1 Mode BC MT RTU ILLEGAL Figure 8 - Configuration Register Aeroflex Circuit Technology 8 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 15 14 13 12 11 10 9 8 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 LOOP TEST FAIL RESPONSE TIME OUT (BC ONLY) FORMAT ERROR STATUS SET (BC ONLY) ERROR FLAG CHB/CHA (RTU ONLY) SOM EOM Note: In BC mode Bit 13, CHB/CHA contains a logic "0" regardless of which channel is used. Figure 5 - Block Status Word CONFIGURATION REGISTER 15 13 0 STACK POINTERS DESCRIPTOR STACKS DATA BLOCKS CURRENT AREA B/A BLOCK STATUS WORD TIME TAG WORD RESERVED MESSAGE BLOCK ADDR DATA BLOCK Note: User may opt to share memory block(s). DATA BLOCK Figure 6 - Use of Descriptor Stack - BC Mode CONFIGURATION REGISTER 15 13 0 (1) STACK POINTERS DESCRIPTOR STACKS LOOK-UP TABLE (DATA BLOCK ADDR) DATA BLOCKS CURRENT AREA B/A BLOCK STATUS WORD TIME TAG WORD RESERVED RECEIVED COMMAND WORD LOOK-UP TABLE ADDR (2) DATA BLOCK Note: (1) User may opt to share memory block(s). (2) See Figure 19. DATA BLOCK Figure 7 - Use of Descriptor Stack - RTU Mode Aeroflex Circuit Technology 9 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 INTERRUPT MASK REGISTER This register is an eight bit read/write register used to enable the interrupt conditions. All interrupts are enabled with a logic "1" (See Figure 9). 15 1 1 1 1 1 1 1 NOT USED BC EOM FORMAT ERROR/STATUS SET NOT USED EOM 4 3 2 1 0 INTERRUPT EOM FORMAT ERROR/ STATUS SET DEFINITION End of Message. Set by CT2566 (during BC or RTU mode) every time a 1553 message is transferred (regardless of validity). Set by CT2566 for these conditions: Loop Test Failure: Last transmitted word did not match received word. Message Error: Received message contained an address error, one of eight 1553 status bits set, or 1553 specification violated (parity error, Manchester error, etc). Time-Out: Expected transmission was not received during allotted time Status Set: Received status word contained status bit(s) set or address error. Bus Controller End of Message. Set by CT2566 (in BC mode) when all messages have been transferred. BC EOM Figure 9 - Interrupt Mask Register START/RESET REGISTER Only two bits of this write only register are used, as illustrated in Figure 10. 15 NOT USED CONTROLLER START RESET 1 0 BIT RESET CONTROLLER START DEFINITION Issued by the CPU to place the CT2566 in the power-on condition; Configuration, and Interrupt Mask registers are reset to logic "0". Issued by the CPU (BC mode) to start message transmission. The CPU must first load the number of messages to transfer (256, max) in the message count location of RAM (area A or B). Value is loaded in 1's complement (load FFFE to transmit one message). In MT mode it is used to begin reception of 1553 messages. Issued by CPU in MT mode to enable monitor operation. Figure 10 - Start/Reset Register Aeroflex Circuit Technology 10 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 BC Operation The BC mode is selected by setting the two MSBs of the Configuration Register to logic "0". This can be done by writing directly to the register or by issuing a MSTRCLR or RESET command. Note that a RESET will also clear the Interrupt Mask Register. BC Initialization. For BC operation, the user initializes the RAM as shown in Table 3 and follows the steps in Figure 11, BC Initialization. The CPU loads the data blocks with 1553 messages (See Figure 12). The first word of each data block must contain the Control Word (shown in Figure 13) for the message. The starting addresses of the data blocks are placed in the fourth word of the Descriptor Stack in the order the messages are to be transmitted (i.e. the address of the first message is loaded into the fourth location of the Stack, the address of the second message is placed into the eighth location, etc). Once the data blocks and the Descriptor Stack have been initialized, the CPU loads the current area message count with the number of messages to transfer (load in 1's complement). CONTROL WORD CONTROL WORD CONTROL WORD CONTROL WORD Table 3 - Typical BC Memory Map (4K memory)] HEX ADDRESS Fixed Areas 0100 0101 0104 0105 0108-013F 0140-017F 0180-01BF 01C0-01FF * * 0F00-0FFF 0000-00FF Stack Pointer A Message Count A Stack Pointer B Message Count B User Defined Areas Not Used Data Block 1 Data Block 2 Data Block 3 * * Descriptor Stack A Descriptor Stack B FUNCTION CONTROL WORD CONTROL WORD CONTROL WORD BROADCAST COMMAND BROADCAST COMMAND (NO DATA) RECEIVE COMMAND TRANSMIT COMMAND RECEIVE COMMAND MODE COMMAND MODE COMMAND MODE COMMAND DATA WORD 1 BROADCAST COMMAND LOOPED BACK BY CT2565 BROADCAST COMMAND (NO DATA) DATA WORD 1 TRANSMIT COMMAND LOOPED BACK BY CT2565 TRANSMIT COMMAND DATA WORD MODE COMMAND LOOPED BACK BY CT2565 MODE COMMAND LOOPED BACK BY CT2565 DATA WORD 2 DATA WORD 2 STATUS RECEIVED TRANSMIT COMMAND LOOPED BACK BY CT2565 DATA WORD LOOPED BACK BY CT2565 STATUS WORD STATUS WORD DATA WORD LAST DATA WORD LAST DATA WORD 1 STATUS WORD 1 FROM XMTR STATUS WORD DATA WORD RECEIVED MODE CODE WITHOUT DATA DATA WORD LOOPED BACK BY CT2565 DATA WORD LAST LOOPED BACK BY CT2566 DATA WORD 2 DATA WORD 1 RECEIVED MODE CODE WITH DATA RECEIVE DATA BLOCK FORMAT MODE CODE WITH DATA TRANSMIT DATA BLOCK FORMAT BROADCAST COMMAND WITH DATA STATUS RECEIVE DATA WORD LAST DATA WORD 2 RECEIVED RECEIVE DATA BLOCK TRANSMIT DATA BLOCK LAST DATA WORD RECEIVED STATUS WORD 2 FROM RECEIVER REMOTE TERMINAL TO REMOTE TERMINAL DATA BLOCK Figure 12 - BC Message Data Block Formats Aeroflex Circuit Technology 11 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 The CPU selects an internal register by asserting MEM/REG and the A2 bit to logic "0" (See Table 2). External registers are selected by asserting MEM/REG logic "0" and A2 bit to a logic "1". The signals EXTEN and EXTLD are used to read and write from the external registers (See Figures 26 to 28). 1. Reads the Stack Pointer to get the address of the current Descriptor Stack Entry. START ISSUE RESET COMMAND Configuration Register The Configuration Register is an eight bit read/write register used to define the 1553 operating mode (BC, MT, or RTU) and the associated RTU status bits. The four MSBs define the mode of operation; the four LSBs define the RTU status bits (See Figure 8). All bits in the Configuration Register (except bit 12) will be present on the respective CT2566 output pins to the 1553 device. The MT bit is inverted at the output. To begin transferring messages onto the bus, the CPU must issue a Controller Start Command (See Figure 14). This is done by setting bit 1 of the Start/Reset Register to a logic "1". An EOM interrupt will be generated each time a message transfer has been completed. A BCEOM will be generated once the specified number of messages has been transferred (message counter = FFFF). A Format Error Status Set Interrupt will be generated at the end of a message if a timeout condition or error condition was detected. If the STOP ON ERROR bit in the Configuration Register is set, the CT2566 will stop bus transactions until a new Controller Start command is issued by the CPU. These interrupts may be masked by the CPU through the Interrupt Mask Register. INITIALIZE STACK POINTER LOAD MESSAGE COUNTER LOAD EVERY FOURTH LOCATION OF STACK WITH STARTING ADDRESS LOAD MESSAGES SET CONFIGURATION RESISTER TO BC MODE INITIALIZE INTERRUPT MASK REGISTER ISSUE START COMMAND Figure 11 BC Initialization (under user control) BC START SEQUENCE After setting the CONTROLLER START bit in the Start/Reset Register, the CT2566 takes the following actions: 1. Reads the Stack Pointer to get the address of the current Descriptor Stack Entry. 2. Stores an SOM flag in the Block Status Word to indicate a transfer operation is in progress. 3. Stores the Time Tag if used. 4. Reads the Data Block Address from the fourth location of the Descriptor Stack and transfers the Data Block Address into an internal Address Register. 5. Issues a BCSTART pulse to the associated 1553 device to start the message transfers. Note that data words are transferred to an from memory by the associated 1553 interface unit using the internal Address Register. 15 NOT USED BUS CHANNEL A/B NOT USED MASK BROADCAST BIT NOT USED MODE CODE BROADCAST RTU TO RTU 8 7 0 BC EOM Sequence. Upon completion of a 1553 message (valid or invalid) the 1553 interface unit issues an EOM pulse to the CT2566 which takes the following actions: Note: When the BC expects the BROADCAST bit set in the status word, a logic "1" will mask the status interrupt error flag. A FORMAT error will be generated if the MASK BROADCAST bit is not set. Figure 13 - BC Control Word 12 Aeroflex Circuit Technology SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 * CONTROLLER START COMMAND RECEIVED READS STACK POINTER LOAD BLOCK STATUS WORD INTO FIRST WORD OF DESCRIPTOR STACK ENTRY (SET SOM BIT IN BLOCK STATUS WORD) LOAD TIME TAG INTO SECOND WORD OF DESCRIPTOR STACK ENTRY DATA BLOCK TRANSFERRED OK ? NO YES OBTAIN DATA BLOCK ADDRESS FROM FOURTH WORD STOP ON ERROR SET ? YES NO ISSUE BC START TO 1553 DEVICE MORE MESSAGES TO SEND ? NO ISSUE BC EOM YES READ CONTROL WORD TO DETERMINE TYPE OF TRANSFER TRANSFER DATA TO/FROM 1553 BUS (NOTE: RAM NOW CONTROLLED BY INPUT PINS CS AND OE STOP UPDATE BLOCK STATUS WORD UPDATE TIME TAG INCREMENT STACK POINTER BY FOUR. DECREMENT MESSAGE COUNT * After controller start is issued the subsystem must wait until BCEOM is active before issuing the next controller start. Figure 14 - BC Sequence of Operation (Under CT2566 Control) Aeroflex Circuit Technology 13 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 2. Updates the Block Status Word by resetting the SOM and setting EOM and any error bits. 3. Updates the Time Tag if used. 4. Increments the contents of the Stack Pointer by four and increments the Message Counter by one. 5. Initiates a message transfer beginning with new Controller Start sequence if more messages are to be transmitted. 6. Generates a BCEOM interrupt if enabled and no further messages are to be transmitted. Note that if an error is received and STOP ON ERROR is set, the CT2566 completes the current BCEOM sequence and then stops. The Stack Pointer will point to the next message to be transmitted. Table 4 - Typical RTU memory map (4K memory) HEX ADDRESS FUNCTION Fixed Areas 0100 0101 0104 0105 0108-013F 0140-017F 01C0-01FF Descriptor Stack Pointer A Reserved Descriptor Stack Pointer B Reserved Spare Look-Up Table A Look-Up Table B User Defined Areas 0180-019F 01A0-01BF 0200-021F 0220-023F 0240-025F 0260-027F * * 0EE0-0EFF 0000-00FF 0F00-0FFF Data Block 1 Data Block 2 Data Block 3 Data Block 4 Data Block 5 Data Block 6 * * Data Block 107 Descriptor Stack A Descriptor Stack B RTU Operation The RTU mode is selected by setting bit 15 of the Configuration Register to logic "1" and bit 14 to logic "0". RTU Initialization For RTU operation, the user initializes the RAM as shown in Table 4 and follows the steps shown in Figure 15, RTU Initialization Chart. Look-Up Tables The first 32 words of the Look-Up Table are initialized with the addresses of the data blocks to be used when received data from subaddress 0, 1, 2,...31. The next 32 table locations should be initialized with the address of the data blocks to be used when the RTU is instructed to transmit data from subaddress 0, 1, 2,...31. The data blocks may be any length sufficient to contain the particular message as long as the data block does not cross a 256 word boundary. Data blocks may be shared by Look-Up Tables A and B, if desired by the user (See Figure 16). The 1553 device can only access the current Look-Up Table and the current Descriptor Stack. The CPU selects the current area through bit 13 of the Configuration Register. Once in the RTU mode, the CT2566 will store the command word in the fourth location of the current area Descriptor Stack. The status of the message will be recorded in the first location of the stack. The data associated with the message will be transferred to/from the data block indicated by the Look-Up Table entry for that subaddress. If a system Time Tag is provided by the user the CT2566 will record the time of the SOM sequence in the second word of the Stack entry. When the CT2566 received an EOM pulse from the 1553 device, it resets the SOM bit in the Block Status Word and sets the EOM bit and any error bits as necessary. The Time Tag entry will be updated and an EOM interrupt will be generated by the CPU, if enabled. 15 87654 1 0 00000000 CURRENT AREA B/A (CONFIG. REG BIT 13) TR (FROM COMMAND WORD) RTU SUBADDRESS BITS (FROM COMMAND WORD) RTU LOOK-UP TABLE ADDRESS RTU SOM Sequence Initiated when 1553 terminal puts a 1553 command word on D00-D15 and pulses SOM low. The CT2566 saves the command received in an internal register. Figure 17 illustrates the RTU Sequence of Operation once a 1553 command word is received. Once the command word is received, the CT2566 performs the following steps: 1. Reads the Stack Pointer to get the address of the current Descriptor Stack Entry. 2. Stores a SOM flag in the Block Status Word to indicate a transfer operation is in progress. 3. Stores the Time Tag if used. Aeroflex Circuit Technology 14 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 4. Stores the Command Word received. 5. Reads a Block address from the Look-Up Table using the T/R bit and the subaddress from the Command Word; transfers the Block address into the address register. Data words are transferred to/from memory by the associated 1553 interface unit using the address register. START ISSUE RESET COMMAND RTU EOM Sequence At the end of a 1553 message (valid or invalid) the CT2566 received an EOM pulse and then performs the following: 1. Updates the Block Status Word. 2. Updates the Time Stage if used. 3. Increments the Stack Pointer by four. 4. Generates an Error Interrupt if enabled. 1553 COMMAND WORD RECEIVED INITIALIZE STACK POINTER SET UP LOOK-UP TABLE(S) DATA BLOCK ASSIGNMENTS SET UP DATA BLOCKS SET CONFIGURATION REGISTER TO RTU MODE READ STACK POINTER INITIALIZE INTERRUPT MASK REGISTER UPDATE DESCRIPTOR STACK BLOCK STATUS WORD, TIME TAG AND COMMAND WORD WAIT FOR 1553 COMMAND Figure 15 RTU Initialization (under user control) READ LOOK-UP TABLE USING T/R SUBADDRESS CURRENT AREA BIT B/A TRANSFER DATA TO/FROM 1553 INTERFACE DEVICE MESSAGE COMPLETE ? YES UPDATE BLOCK STATUS WORD AND TIME TAG NO RECEIVED COMMAND WORD RTU WORD ADDR T/R SUBADD COUNT XXXXX 0 00000 XXXXX LOOK-UP TABLE USER DEFINED 0140 USER DEFINED 0141 INCREMENT STACK POINTER BY FOUR XXXXX 0 00001 XXXXX XXXXX 0 00010 XXXXX USER DEFINED 0142 GENERATE EOM INTERRUPT AND ERROR INTERRUPT IF ERROR CONDITION DETECTED XXXXX 1 11110 XXXXX USER DEFINED 017E USER DEFINED 017F XXXXX 1 11111 XXXXX EXIT } 64 LOCATIONS Figure 17 - RTU Sequence of Operation (under CT2566 control) Aeroflex Circuit Technology Figure 16 - RTU Look-up Table 15 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 MT Operation The MT mode is selected by setting bit 15 of the Configuration Register to logic "0" and bit 14 to a logic "1" along with issuing a Controller Start Command. Word. The RAM automatically wraps around (from location FFFF to location 0000), shown in Figure 20. Bit 7 of the Identification Word can be reset by the CPU each time it reads the associated data word into CPU memory. This provides a simple method of keeping track of words that have been processed by the CPU. 15 1 87 111 GAP TIME SET TO "1" START 0 ISSUE RESET COMMAND CLEAR RAM ERROR (1 = ERROR, 0 = GOOD STATUS) COMMAND SYNC 1553 CHANNEL A/B INITIALIZE STACK POINTER WORD GAP SET TO "0" SET CONFIGURATION REGISTER TO MT MODE Note: Each bit of the GAP TIME field represents .5s. Figure 19 - MT Identification Word ISSUE START COMMAND Figure 18 - MT Initialize (under user control) START COMMAND ISSUED MT Initialization For MT operations, the entire RAM is used as the MT Stack (See Table 5) and the setups shown in Figure 18 are followed. The user instructs the CT2566 where to store the first received 1553 word by loading the starting word address in the Stack Pointer. Once a Controller Start command is issued, the CT2566 will store this value in the internal Address Register. The identification Word provides the CPU with additional information regarding the received 1553 word, its format is shown in Figure 19. This information allows the user to develop algorithms to restructure the message transfers. External Logic can be used for triggering on specific commands or subaddresses. For further information, consult factory. The 1553 device will generate an Identification Word for every word that is transferred across the 1553 Data Bus. The CT2566 stores the received 1553 word in the RAM location indicated by the internal Address Register. The contents of this register are incremented by one so that it points to the next word in RAM, and the Identification Word is stored at that location. The internal Address Register is then incremented by one again, in preparation for storing the next Identification GET STACK POINTER FROM WORD 100 IN RAM AND STORE IN INTERNAL REGISTER WORD TRANSFERRED ACROSS 1553 BUS ? YES STORE RETREIVED 1553 WORD IN RAM, INCREMENTS INTERNAL ADDRESS REGISTER NO STORE IDENTIFICATION WORD IN RAM, INCREMENT INTERNAL ADDRESS REGISTER Figure 20 - MT Sequence of Operation (under CT2566 control) Aeroflex Circuit Technology 16 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 Table 5 - Typical MT memory map (4K memory) HEX ADDRESS FUNCTION First Received 1553 Word First Identification Word Second Received 1553 Word Second Identification Word 0000 0001 0002 0003 0004 0005 0006 0007 0008 * * 0100 0104 * * FFFF * * * * * * * Stack Pointer A (Fixed location)* Stack Pointer B MODE CODES All mode codes applicable to dual redundant systems are recognized by the CT2566. Mode codes can be illegalized by the 1553 BC or RTU device. Refer to the CT2565 or CT2512 data sheets for more information. * * Word stored at FFFF will be followed by the word stored at 0000. * The Stack Pointer is loaded into an internal Address Register upon receipt of a Controller Start command. This location is overwritten by data once monitor operation begins. CT2566 Timing Clock in at 12 MHz Figures 21 through 37 illustrate the timing for the CT2566 and its operation. All timing definitions are listed in the tables below and the appropriate definitions are repeated with each diagram. Delay Timing SYMBOL td1 td2 td3 td4 td5 td6 td7 td8 td9 td10 DESCRIPTION READYD low delay (CPU Handshake) IOEN high delay (CPU Handshake) CPU MEMWR low delay CPU MEMOE low delay EXTLD low delay RESET low delay Internal Register delay (read) Internal Register delay (write) Register Data/Address set-up time Register Data/Address hold time 17 MIN - MAX 200 20 120 115 130 30 60 60 40 0 UNITS ns ns ns ns ns ns ns ns ns ns Aeroflex Circuit Technology SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 Delay Timing (Cont.) SYMBOL td11 td12 td13 td14 td15 td16 td17 td18 td19 td20 td21 td22 td23 DESCRIPTION BC SOM Cycle DMA delay INT low delay RTU SOM Cycle DMA delay 1553 Command Word set-up time 1553 Command Word hold time MT SOM Cycle DMA delay CS low to MEMCS low delay OE low to MEMOE low delay WR low to MEMWR low delay BUSGRNT high delay BUSACK low Address delay BUSACK high Address delay Address increment delay MIN 60 60 - MAX 120 50 200 120 30 30 30 25 45 25 200 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns Pulse Width Timing SYMBOL tpw1 tpw2 tpw3 tpw4 tpw5 tpw6 tpw7 tpw8 tpw9 tpw10 tpw11 tpw12 tpw13 tpw14 tpw15 DESCRIPTION READYD pulse width (CPU Handshake) CPU MEMWR low pulse width CPU MEMCS low pulse width EXTLD low pulse width RESET low pulse width DMA MEMWR low pulse width DMA MEMCS low pulse width BCSTART low pulse width EOM low pulse width INT low pulse width INT low (BCEOM) pulse width SOM low pulse width NBGRNT low pulse width ADRINC low pulse width MSTRCLR low pulse width MIN 70 70 70 70 70 70 70 70 50 * 60 50 50 50 150 MAX 200 tpw9 200 200 200 - UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *The min value of tpw10 equals tpw9 minus 30 ns. 18 Aeroflex Circuit Technology SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 12MHz Clock (Internal) STRBD (41) See Note SELECT (1) td1 IOEN (42) td7 READYD (3) tpw1 MEM/REG (10) td2 RD/WR (2) A02 (38) A01 (77) A00 (39) SSFLAG, SSBUSY, SVCRQST DBAC, RTU/BC, MT, CTLIN B/A D15-D00 DATA VALID NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus. CPU Reads from Internal Register SYMBOL td1 td2 tpw1 td7 DESCRIPTION READYD low delay (CPU Handshake) IOEN high delay (CPU Handshake) READYD pulse width (CPU Handshake) Internal Register delay (read) MIN 70 - MAX 200 20 60 UNITS ns ns ns ns Figure 21 - CPU reads from internal register Aeroflex Circuit Technology 19 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 12MHz Clock (Internal) See Note STRBD (41) SELECT (1) td1 IOEN (42) td9 READYD (3) tpw1 td2 MEM/REG (10) RD/WR (2) A02 (38) A01 (77) A00 (39) td8 SSFLAG, SSBUSY, SVCRQST DBAC, RTU/BC, MT, CTLIN B/A D15-D00 DATA LATCHED Configuration Register Only DATA VALID td10 NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus. CPU Writes to Internal Register SYMBOL td1 td2 tpw1 td8 td9 td10 DESCRIPTION READYD low delay (CPU Handshake) IOEN high delay (CPU Handshake) READYD pulse width (CPU Handshake) Internal Register delay (write) Register Data/Address set-up time Register Data/Address hold time MIN 70 - MAX 200 20 60 40 0 UNITS ns ns ns ns ns ns Figure 22 - CPU writes to internal register Aeroflex Circuit Technology 20 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 12MHz Clock (Internal) See Note STRBD (41) SELECT (1) td1 IOEN (42) td9 READYD (3) tpw1 td2 MEM/REG (10) RD/WR (2) A02 (38) A01 (77) A00 (39) EXTEN (4) D15-D00 DATA FROM EXTERNAL REGISTER NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus. CPU Reads from External Register Timing SYMBOL td1 td2 tpw1 td9 DESCRIPTION READYD low delay (CPU Handshake) IOEN high delay (CPU Handshake) READYD pulse width (CPU Handshake) Register Data/Address set-up time MIN 70 - MAX 200 20 40 UNITS ns ns ns ns Figure 23 - CPU reads from external register Aeroflex Circuit Technology 21 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 12MHz Clock (Internal) See Note STRBD (41) SELECT (1) td1 IOEN (42) td9 READYD (3) tpw1 td10 td2 MEM/REG (10) RD/WR (2) A02 (38) A01 (77) A00 (39) td5 EXTLD (43) VALID VALID tpw4 D15-D00 CPU DATA NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus. CPU Writes to External Register SYMBOL td1 td2 tpw1 td5 td9 td10 tpw4 DESCRIPTION READYD low delay (CPU Handshake) IOEN high delay (CPU Handshake) READYD pulse width (CPU Handshake) EXTLD low delay Register Data/Address set-up time Register Data/Address set-up time EXTLD low pulse width MIN 70 70 MAX 200 20 130 40 0 - UNITS ns ns ns ns ns ns ns Figure 24 - CPU writes to external register Aeroflex Circuit Technology 22 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 12MHz Clock (Internal) See Note STRBD (41) SELECT (1) IOEN (42) td1 READYD (3) tpw1 td2 MEM/REG (10) RD/WR (2) MEMCS (16) MEMOE (56) td4 A15-A00 D15-D00 RAM ADDRESS VALID RAM DATA VALID NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus. CPU Reads from Ram SYMBOL td1 td2 tpw1 td9 DESCRIPTION READYD low delay (CPU Handshake) IOEN high delay (CPU Handshake) READYD pulse width (CPU Handshake) CPU MEMOE low delay MIN 70 - MAX 200 20 115 UNITS ns ns ns ns Figure 25 - CPU reads from RAM Aeroflex Circuit Technology 23 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 12MHz Clock (Internal) See Note STRBD (41) SELECT (1) IOEN (42) td1 READYD (3) tpw1 td2 MEM/REG (10) RD/WR (2) MEMCS (16) tpw3 td3 MEMWR (57) tpw2 A15-A00 RAM ADDRESS VALID RAM DATA VALID D15-D00 NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus. CPU Writes To Ram SYMBOL td1 td2 tpw1 td3 tpw2 tpw3 DESCRIPTION READYD low delay (CPU Handshake) IOEN high delay (CPU Handshake) READYD pulse width (CPU Handshake) CPU MEMWR low delay CPU MEMWR low pulse width CPU MEMCS low pulse width MIN 70 70 70 MAX 200 20 120 - UNITS ns ns ns ns ns ns Figure 26 - CPU writes to RAM Aeroflex Circuit Technology 24 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 BUSREQ (13) BUSGRNT (14) td20 BUSACK (53) A15-A00 td2 td22 MIL-STD-1553 TO CT2566 Handshaking SYMBOL td20 td21 td22 DESCRIPTION BUSGRNT high delay BUSACK low Address delay BUSACK high Address delay MIN - MAX 25 45 25 UNITS ns ns ns Figure 27 - MIL-STD-1553 to CT2566 Handshaking CS (55) MEMCS (16) OE (17) MEMOE (56) WR (54) MEMWR (57) td17 td18 td19 MIL-STD-1553 Terminal to Delay SYMBOL td17 td18 td19 DESCRIPTION CS low to MEMCS low delay OE low to MEMOE low delay WR low to MEMWR low delay MIN - MAX 30 30 30 UNITS ns ns ns Figure 28 - MIL-STD-1553 terminal I/O delay Aeroflex Circuit Technology 25 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 BUSACK (53) td14 ADRINC (9) A15-A00 ADDRESS td23 ADDRESS + 1 CT2566 Address Increment SYMBOL tpw14 td23 DESCRIPTION ADRINC low pulse width Address increment delay MIN 50 - MAX 200 200 UNITS ns ns Figure 29 - CT2566 Unit Address Increment tpw15 MSTRCLR (52) See Note RESET (47) td6 CT2566 Direct Increment SYMBOL td6 tpw15 DESCRIPTION RESET low delay MSTRCLR low pulse width MIN 150 MAX 30 - UNITS ns ns NOTE: The RESET (low) pulse width will be approximately equal to that of MSTRCLR (low). Figure 30 - CT2566 direct reset Aeroflex Circuit Technology 26 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 12MHz Clock (Internal) See Note STRBD (41) SELECT (1) IOEN (42) td1 READYD (3) tpw1 MEM/REG 10) td2 RD/WR (2) A02 (38) A01 (77) A00 (39) D00 (67) RESET (47) tpw5 NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus. Programmed CT2566 Reset SYMBOL td1 td2 tpw1 tpw5 DESCRIPTION READYD low delay (CPU Handshake) IOEN high delay (CPU Handshake) READYD pulse width (CPU Handshake) RESET low pulse width MIN 70 70 MAX 200 20 - UNITS ns ns ns ns Figure 31 - Programmed CT2566 reset Aeroflex Circuit Technology 27 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 Aeroflex Circuit Technology 12 MHz Clock (Internal) STRBD (41) SELECT (1) IOEN (42) READYD (3) MEM/REG (10) RD/WR (2) A02 (38) A01 (77) A00 (39) D01 (28) MEMCS (16) MEMWR (57) MEMOE (56) td9 td10 td11 28 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 TAGEN (5) tpw8 BCSTART (46) A15-A00 D15-D00 STACK POINTER STACK ADDRESS STACK ADDRESS BLOCK STATUS WORD STACK ADDRESS + 1 TIME TAG STACK ADDRESS + 2 TRI-STATE STACK ADDRESS + 3 BLOCK ADDRESS BC SOM Timing (No Contention) SYMBOL td9 td10 td11 tpw8 DESCRIPTION Register Data/Address set-up time Register Data/Address hold time BC SOM Cycle DMA delay BCSTART low pulse width MIN 70 MAX 40 0 120 - UNITS ns ns ns ns Figure 32 - BC SOM timing (no contention) BC EOM Timing (No Contention) SYMBOL td9 tpw9 tpw10 tpw11 DESCRIPTION INT low delay INT low pulse width INT low pulse width INT low delay MIN 50 * 60 MAX 50 200 tpw9 - UNITS ns ns ns ns * The min value of tpw10 equals tpw9 minus 30ns. 12 MHz Clock (Internal) EOM (6) tpw9 MEMCS (16) MEMWR (57) MEMOE (56) TAGEN (5) INT (45) A15-A00 D15-D00 td12 EOM/Error tpw10 STACK POINTER STACK ADDRESS STACK ADDRESS BLOCK STATUS WORD STACK ADDRESS + 1 TIME TAG STACK ADDRESS + 2 TRI-STATE STACK ADDRESS + 3 TRI-STATE Figure 33 - BC EOM timing (no contention) tpw11 BC STACK POINTER STACK ADDRESS + 4 STACK POINTER + 1 MESSAGE COUNT STACK POINTER + 2 TRI-STATE STACK POINTER + 1 MESSAGE COUNT + 1 EOM Figure 33 - BC EOM timing (no contention) con't Aeroflex Circuit Technology 29 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 Aeroflex Circuit Technology td13 SOM (7) NBGRNT (19) MEMCS (16) MEMWR (57) MEMOE (56) TAGEN (5) BCSTART (46) A15-A00 td14 D15-D00 td15 1553 COMMAND WORD STACK POINTER STACK ADDRESS STACK ADDRESS BLOCK STATUS WORD STACK ADDRESS + 1 TIME TAG STACK ADDRESS + 2 TRI-STATE STACK ADDRESS + 3 COMMAND LOOK-UP ADDRESS BLOCK ADDRESS tpw8 tpw12 tpw13 30 RTU SOM Timing (No Contention) SYMBOL td13 td14 td15 tpw8 tpw12 tpw13 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 DESCRIPTION RTU SOM Cycle DMA delay 1553 Command Word set-up time 1553 Command Word hold time BCSTART low pulse width SOM low pulse width NBGRNT low pulse width MIN 60 60 70 50 50 MAX 200 200 200 UNITS ns ns ns ns ns ns Figure 34 - RTU SOM (no contention) Aeroflex Circuit Technology 12 MHz Clock (Internal) EOM (6) MEMCS (16) MEMWR (57) MEMOE (56) TAGEN (5) INT (45) tpw10 A15-A00 D15-D00 STACK POINTER STACK ADDRESS STACK ADDRESS BLOCK STATUS WORD STACK ADDRESS + 1 TIME TAG STACK ADDRESS + 2 TRI-STATE STACK ADDRESS + 3 TRI-STATE STACK POINTER STACK ADDRESS + 4 tpw9 31 RTU EOM Timing (No Contention) SYMBOL SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 DESCRIPTION RESET low delay MSTRCLR low pulse width MIN 50 * MAX 200 tpw9 UNITS ns ns tpw9 tpw10 * The min value of tpw10 equals tpw9 minus 30ns. Figure 35 - RTU EOM timing (no contention) 12 MHz Clock (Internal) STRBD (41) SELECT (1) IOEN (42) READYD (3) MEM/REG (10) RD/WR (2) A02 (38) A01 (77) A00 (39) D01 (28) td16 MEMCS (16) MEMOE (56) BCSTART (46) tpw6 A15-A00 STACK POINTER D15-D00 STACK ADDRESS MT SOM Timing (No Contention) SYMBOL td16 tpw6 DESCRIPTION MT SOM Cycle DMA delay BCSTART low pulse width MIN 70 MAX 120 - UNITS ns ns Figure 36 - MT SOM timing (no contention) Aeroflex Circuit Technology 32 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 12 MHz Clock (Internal) MEMCS (16) tpw6 MEMOE (56) MEMWR (57) tas2 tah2 tas1 tpw7 tah1 A15-A00 D15-D00 tds2 tdh2 tds1 tdh1 DMA READ DMA WRITE DMA Read/Write Timing (SOM/EOM Cycles) SYMBOL tas1 tah1 tds1 tdh1 tas2 tah2 tds2 tdh2 tpw6 tpw7 DESCRIPTION DMA Address set-up time DMA Address hold time DMA Address set-up time DMA Address hold time DMA Address set-up time DMA Address hold time DMA Address set-up time DMA Address hold time DMA MEMWR low pulse width DMA MEMCS low pulse width MIN 40 60 83 30 0 0 70 70 MAX 45 83 - UNITS ns ns ns ns ns ns ns ns ns ns Figure 37 - DMA Read/Write timing (SOM/EOM cycles) Aeroflex Circuit Technology 33 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 Table 6 - CT2566 Pin Out Description (DDIP) Pin # 1 2 3 Function SELECT RD/WR READYD EXTEN TAGEN EOM SOM STATERR ADRINC MEM/REG CLOCK IN LOOPERR BUSREQ BUSGRNT N/C MEMCS OE N/C NBGRNT + 5 Volt D15 D13 D11 D09 D07 D05 D03 D01 SSFLAG SSBUSY RTU/BC A14 A12 A10 A08 A06 A04 A02 A00 Pin # 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Function GND STRBD IOEN EXTLD CHB/CHA INT BCSTART RESET MSGERR CTLIN B/A CTLOUT B/A TIMEOUT MSTRCLR BUSACK WR CS MEMOE MEMWR N/C MT D14 D12 D10 D08 D06 D04 D02 D00 SVCREQ DBAC A15 A13 A11 A09 A07 A05 A03 A01 GND 1 41 2 42 3 43 4 44 5 45 6 46 7 47 8 48 9 49 10 50 11 51 12 52 13 53 14 54 15 55 16 56 17 57 18 58 19 59 20 SELECT STRBD RD/WR IOEN READYD EXTLD EXTEN CHB/CHA TAGEN INT EOM BCSTART SOM RESET STATERR MSGERR ADRINC CTLIN B/A MEM/REG CTLOUT B/A CLOCK IN TIMEOUT LOOPERR MSTRCLR BUSREQ BUSACK BUSGRNT WR N/C CS MEMCS MEMOE OE MEMWR CT2566 MIL-STD-1553 to PROCESSOR INTERFACE UNIT N/C N/C NBGRNT MT +5 Volt D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 SSFLAG SVCREQ SSBUSY DBAC RTU/BC A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 GND GND 21 60 22 61 23 62 24 63 25 64 26 65 27 66 28 67 29 68 30 69 31 70 32 71 33 72 34 73 35 74 36 75 37 76 38 77 39 78 40 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 DDIP Pin Connection Diagram, CT2566 and Pinout Aeroflex Circuit Technology 34 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 Table 7 - CT2566 Pin Out Description (FP) Pin # 1 2 3 Function N/C SELECT STRBD RD/WR IOENBL READYD EXTLD EXTEN CHB/CHA TAGEN INT EOM BCSTART SOM RESET STATERR MSGERR ADRINC CTLIN B/A MEM/REG CTLOUT B/A CLOCK IN TIMEOUT LOOPERR MSTRCLR BUSYREQ BUSACK BUSGRNT WR N/C CS MEMCS MEMOE OE MEMWR N/C N/C NBGRNT MT +5V N/C Pin # 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Function N/C GROUND CASE GND A00 (LSB) A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 RTU/BC DBAC SSBUSY SVCREQ SSFLAG D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 N/C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 N/C SELECT STRBD RD/WR IOENBL READYD EXTLD EXTEN CHB/CHA TAGEN INT EOM BCSTART SOM RESET STATERR MSGERR ADRINC CTLIN B/A MEM/REG CTLOUT B/A CLOCK IN TIMEOUT LOOPERR MSTRCLR BUSYREQ BUSACK BUSGRNT WR N/C CS MEMCS MEMOE OE MEMWR N/C N/C NBGRNT MT +5V N/C N/C CT2566FP MIL-STD-1553 to PROCESSOR INTERFACE UNIT D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 SSFLAG SVCREQ SSBUSY DBAC RTU/BC A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 (LSB) CASE GND GROUND N/C 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Flat Package Pin Connection Diagram, CT2566 and Pinout Aeroflex Circuit Technology 35 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 Plug In Package Outline 2.100 1.870 Lead 1 & ESD Designator .100 .110 Pin 1 Pin 2 1.900 .050 Pin 19 TYP Pin 20 Pin 59 Pin 41 .018 DIA TYP .250 MAX 1.650 1.500 Pin 60 Pin 78 Pin 21 Pin 22 .100 TYP Pin 39 Pin 40 .250 1.800 Flat Package Outline .050 Pin 82 2.200 MAX .015 Pin 42 .010 .002 .180 MAX 1.610 MAX Lead 1 & ESD Designator .400 MIN .095 (4 Places) 2.000 .050 Lead Centers 41 Leads/Side 36 Pin 41 .080 Aeroflex Circuit Technology SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 CIRCUIT TECHNOLOGY Ordering Information Model Number CT2566 CT2566-FP Screening Military Temperature, -55C to +125C, Screened to the individual test methods of MIL-STD-883 DESC SMD # Package Plug in Flat Package Specifications subject to change without notice Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803 www.aeroflex.com/act1.htm Aeroflex Circuit Technology Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: (800) THE-1553 E-Mail: sales-act@aeroflex.com 37 SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700 |
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